1. Technical Field
The present invention relates generally to semiconductor technology and more specifically to semiconductor research and development.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in a wide variety of products, such as televisions, telephones, and appliances.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each worth hundreds or thousands of dollars.
The ideal would be to have every one of the integrated circuits on a wafer functional and within specifications, but because of the sheer numbers of processes and minute variations in the processes, this rarely occurs. “Yield” is the measure of how many “good” integrated circuits there are on a wafer divided by the maximum number of possible good integrated circuits on the wafer. A 100% yield is extremely difficult to obtain because minor variations, due to such factors as timing, temperature, and materials, substantially affect a process. Further, one process often affects a number of other processes, often in unpredictable ways.
In a manufacturing environment, the primary purpose of experimentation is to increase the yield. Experiments are performed in-line and at the end of the production line with both production wafers and experimental wafers. However, yield enhancement methodologies in the manufacturing environment produce an abundance of very detailed data for a large number of wafers in processes subject only to minor variations. Major variations in the processes are not possible because of the time and cost of using production equipment and production wafers. Setup times for equipment and processing time can range from weeks to months, and processed wafers can each contain hundreds of thousands of dollars worth of integrated circuits.
The learning cycle for the improvement of systems and processes requires coming up with an idea, formulating a test(s) of the idea, testing the idea to obtain data, studying the data to determine the correctness of the idea, and developing new ideas based on the correctness of the first idea. The faster the correctness of ideas can be determined, the faster new ideas can be developed. Unfortunately, the manufacturing environment provides a slow learning cycle because of manufacturing time and cost.
Recently, the great increase in the complexity of integrated circuit manufacturing processes and the decrease in time between new product conception and market introduction have both created the need for speeding up the learning cycle.
This has been accomplished in part by the unique development of the integrated circuit research and development environment. In this environment, the learning cycle has been greatly speeded up and innovative techniques have been developed that have been extrapolated to high volume manufacturing facilities.
To speed up the learning cycle, processes are speeded up and major variations are made to many processes. To reduce costs, only a few wafers are actually processed for each cycle. This research and development environment has resulted in the generation of tremendous amounts of data and analysis for all the different processes and variations. This, in turn, has required a large number of engineers to do the analysis. With more data, the answer always has been to hire more engineers.
However, this is not an acceptable solution for major problems. For example, during the production of semiconductor devices, in-line defect inspections are conducted at various times to obtain defect data about the devices. In-line defects are detected by inspection techniques that are conducted between the process steps that fabricate the semiconductor devices. Actual defects are then determined later using various tests after the semiconductor chip fabrication is completed. The defect data is typically collected by electrical testing, by laser scanning, by optical inspection, or by a scanning electron microscope.
Defects may include many different events that may have very different respective impacts on chip yield. Any irregularities, such as structural imperfections, particles, residuals, or embedded foreign material, are considered as defects, along with electrical performance defects.
The inspection techniques often result in a total count of the number of defects detected in each process step, as well as the physical locations of the defects, but not an abundance of in-depth or specific defect data. Total count and location information alone has generally not been sufficient for assigning good yield loss projections to defects detected at each particular process step, nor for correcting and adjusting process operations to reduce or eliminate the defects.
Nevertheless, semiconductor testing is needed for quality control of manufacturing processes and of the products themselves. Typical testing reveals both the types of defects and their locations on the semiconductor wafer. Fail locations during tests on a chip are then typically reported as X-Y coordinates, which are then consolidated into a map called a “bitmap”. This leads to full bitmap techniques or fail vector techniques that may be used to generate and record locations of failures.
Since speed is also critical for efficient manufacturing, it is important to be able to analyze all the test data quickly. Unfortunately, reviewing all the inspected defects, even using known automated classification, can significantly delay yield learning cycles and the subsequent manufacturing process adjustments and corrections for the semiconductor devices.
The challenge is compounded by the additional process data that is generated by the ordinary measuring and testing that is performed during semiconductor fabrication processing. This includes, for example, wafer, die, and wafer lot parameters that are generated during fabrication and post-fabrication measuring and testing.
Correspondingly, the better the inspections during production, the better the data that can then potentially shorten yield learning cycles by making it possible to react quickly to process problems. The process engineer therefore needs to know the number of defects per chip, the X-Y coordinates of each defect, and a set of parameters (different for different tools) that are specific for each particular defect. To obtain yield impact projections, it is then desirable to correlate the actual defect data to actual electrical failures. Such data can be crucial for adjusting manufacturing process parameters to maximize the yields of a product.
However, conventional wafer bitmaps are at the individual chip and bit level. In a production facility, on the other hand, data at the wafer, boat, and/or the lot level would be more meaningful for defect analysis. There is thus a need in production environments to enable wafer, boat, and/or lot level bitmap comparison rather than comparison at the conventional individual bit level. Preferably, bitmap comparison at such elevated levels would provide wafer level global bitmap characterization for improving and accelerating integrated circuit technology development.
Such wafer level global bitmap characterization could provide systems and methods that can use the results from these various tests to quickly compare the wafers, boats, and/or wafer lots. Satisfying these needs would then enable the rapid correlation of defect data and yield data among the wafers, boats, and wafer lots to assist in finding cause-and-effect relationships between process conditions and the measured chip characteristics and parameters. This in turn would provide for rapidly determining appropriate process adjustments and corrections for improving process yields and quality.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.